2+ years hands on experience performing Place & Route (P&R)

Experience with one or more of the following P&R tools is required: Apollo, Silicon Ensemble, Cell3, Gate or Cell Ensemble, Blast Fusion, Dolphin

Experience with the following is strongly preferred: - Floorplanning using tools: Planet, Design Planner, or Preview - Timing Analysis using tools: PrimeTime, or Motive - Interconnect (Parasitic) Extraction using tools: Dracula LPE/PRE, Star-RC, X-Calibre, Fire & Ice - Physical Verification using tools: Diva, Dracula, Calibre, Hercules

Min. four year degree in Electrical Engineering, Computer Science, or equivalent

2+ years hands on experience designing large and complex digital ASIC's

Experience with one or more of the following design tools is required: - RTL coding using VerilogHDL or VHDL - Synthesis using Design Compiler or Ambit Build Gates - Simulation any of the following or equivalent tools: Verilog, SpeedSim, Lsim, Model Sim, VCS, VSS, Leapfrog - Timing analysis using DesignTime, PrimeTime or Motive

Experience with the following is desirable: - Logical Verification at RTL, Gate, and chip level - Floorplanning using tools: Planet, Design Planner, or Preview

Min. four year degree in Electrical Engineering, Computer Science, or equivalent

2+ years hands on experience verifying large and complex digital ASIC's

Experience with the following is required: - Verilog or VHDL languages - Logical Verification at RTL, Gate, and chip level - Testbench development - Simulation using any of the following or equivalent tools: Verilog, SpeedSim, Lsim, Model Sim, VCS, VSS, Leapfrog

Experience with the following is desirable: - Floorplanning using tools: Planet, Design Planner, or Preview - Synthesis using Design Compiler or Ambit Build Gates - Timing analysis using DesignTime, PrimeTime or Motive - Understanding of VERA language · Min. four year degree in Electrical Engineering, Computer Science, or equivalent.